The present invention relates to a circuit that protects the inputs and outputs of a semiconductor devices from damage caused by electrostatic discharge (ESD) and more specifically, to an ESD protection circuit for inputs and outputs of radio frequency semiconductor devices.
In semiconductor devices, device geometry has scaled down with improvements in photolithography and diffusion processing technology. Indeed, it is becoming increasingly common for high-speed semiconductor devices to include millions of transistors where the dimensions of the transistors have been scaled down to sub-micron range. Advantageously, as the dimensions of the transistors (most particularly the channel length) are reduced, the time delay per stage decreases by a corresponding factor. Thus, as transistors are scaled to sub-micron dimensions, the time delay per stage decreases and the circuits may operate at higher clock rates. Accordingly, such semiconductor devices are now commonly used for radio frequency (RF) or microwave frequency applications. Recently, complementary metal-oxide semiconductor (CMOS) devices operating at radio frequencies have minimum transistor geometry on the order of 0.35 microns while some semiconductor devices have more recently been introduced with 0.18 micron minimum geometry.
Unfortunately, semiconductor devices manufactured with channel lengths of 0.35 microns or smaller, are extremely susceptible to damage from high voltages due to very thin gate oxide covering the channel. Such semiconductor devices are particularly susceptible to damage from uncontrolled discharge of accumulated electrostatic charges that readily accumulate on the human body. As will be appreciated by one familiar with semiconductor processing, transistors that interface with "off-chip" devices are most susceptible to damage or degradation from electrostatic discharge (ESD).
Electrostatic charge accumulation on nonconductive bodies is a common phenomenon that has been well documented. Indeed, human-body models are well known in the art describing the extremely high static charge that can build up on a person by friction, electrostatic induction or by other means. A significant problem for manufacturers and users of products that include semiconductor devices is that the human body can generate and accumulate an electrostatic charge that can easily destroy sensitive semiconductor devices when a charged person handles the device. Without protection from the accumulated charge or its suppression, an uncontrolled discharge through one or more inputs or outputs of the semiconductor device can damage or degrade transistors or other electrical components.
For this reason, many semiconductor devices include protection circuits that are designed to shunt the accumulated charge to either the power or the ground bus. One common protection circuit employs large diodes (p-n junctions) coupled between the input or output and a power bus. This diode structure typically protects inputs or outputs from electrostatic discharge up to about 2,500 volts. When an input or output of a semiconductor device is subjected to an electrostatic charge, these diodes will switch to a conductance mode to provide a short circuit path to a power bus to dissipate the surge and then rapidly turn "off."
Such protection circuits are more than adequate for semiconductor devices that operate at relatively low frequencies, for example, at or below 100 MHz. However, for semiconductor devices that operate at high frequencies, it is not possible to depend on the prior art ESD protection circuits because of capacitive loading. It is also well known that the overall performance of a system may be seriously degraded if one or more outputs must drive a large capacitive load. Since the prior art protection circuits noted above may introduce up to several tens of picoFarads (e.g. 100 pF) at each output, the use of such protective circuits is generally avoided in circuit applications that require high signal rates. Further at the higher operating frequencies typically encountered in RF applications, capacitive load tends to act as a low impedance creating signal distortion and low impedance paths to power or ground during normal operation greatly increasing input or output power drain.
For these reasons, many manufacturers of semiconductor devices tend to forego protection from ESD on the high-speed inputs and outputs. Indeed, minimizing the capacitive loading to ensure proper operation of the device at high operating rates is often deemed more important than protecting the device from the potential of ESD-induced damage or degradation. However, without protection on the high-speed inputs and outputs, special handling and storage precautions are required to minimize the potential for damage from ESD.
Unfortunately, such precautions are expensive, time consuming to implement, an annoyance to manufacturing personnel and often ineffective. Thus, without any protection at the signal line, these unprotected signal lines are susceptible to damage from ESD or other voltage transients even when securely mounted on a circuit board. Electrostatic discharge can easily damage or degrade unprotected signal lines to a degree where the device may simply cease to function.
In another prior art protection circuit commonly used in bi-polar semiconductor technology, a pair of NPN transistors couple each input and output to the power buses. FIG. 1 illustrates one technique for connecting such transistors. Specifically, the collector of a first transistor 5 is connected to the most positive power bus (commonly referred to as Vcc) and the emitter is connected to the signal line and the associated input or output circuit 8. In this embodiment the base of transistor 5 is left floating. A second transistor 6 has its collector connected to the circuit 8 and the emitter connected to ground or the most negative power bus (commonly referred to as Vee). The base of transistor 6 is also left floating. In this configuration, transistors 5 and 6 utilize a zener breakdown mechanism to provide ESD protection.
Accordingly, what is needed is an ESD protection circuit for CMOS devices that have one or more high-speed inputs or outputs. The ESD protection circuit must provide protection against a reasonable level of voltage such as is typically generated by a human body or typically encountered in the operating environment. What is further needed is an ESD protection circuit with minimal capacitive loading so as to minimize signal degradation or stray low impedance paths to power or ground. Further still, what is needed is an ESD protection circuit for high-speed inputs and outputs of a CMOS device. Thus, whatever the merits of the above described prior art protection circuits, they do not achieve the benefits of the present invention.